(1) Field of the Invention
The present invention relates to a sampling system which achieves timing recovery in sampling an input signal that is received at a receiving part of a modem. When sampling the received signal, symbol synchronization and carrier synchronization must be derived at the receiving part of the modem, and the present invention particularly relates to the symbol synchronization for the timing recovery.
(2) Description of the Related Art
It is well known that symbol synchronization at a receiving part of a modem when sampling a received signal is important for achieving timing recovery. It is required that in the modem a symbol rate (or baud rate) “fbr” of a received signal and its phase are matched with a symbol rate “fbt” of a transmitted signal and its phase. Usually, the transmitter and the receiver are distant via a communication channel, and a system clock of the transmitter and a system clock of the receiver are independent of each other. The receiving part of the modem is required to derive from the received signal an estimated symbol rate “fbr” that is very close to the system clock frequency and has an arbitrary amount of a timing phase with respect to the system clock phase.
Generally, the received signal is sampled periodically at a sampling rate “fsr” that is a multiple of the symbol rate “fbr”, and subjected to demodulation. The sampling of the received signal is also called analog-to-digital (AD) conversion. In a case of a full-duplex modem, the transmitting operation is controlled by the transmitting part of the modem and the receiving operation is controlled by the receiving part of the modem. That is, in the full-duplex modem in which the receiving part and the transmitting part are concurrently operating, the signal to be transmitted to a communication channel is sampled periodically at a sampling rate “f′sr” that is a multiple of the symbol rate “f′br”. The sampling of the transmitted signal is also called digital-to-analog (DA) conversion.
In the full-duplex modem, there is a problem in that the sampling rate “fsr” and its phase at the receiving part and the sampling rate “f′sr” and its phase at the transmitting part are generally not consistent. It is required that in the full-duplex modem the AD conversion and the DA conversion are independently controlled at timings which are different from each other. Because of this, in a conventional analog front-end LSI, the AD converter and the DA converter are constructed into separate units which independently operate at timings which are different from each other.
Further, in a conventional modem, the AD converter requires an external logic circuit which controls the timing phase of a clock signal. In addition, in a conventional modem, the AD conversion and the DA conversion are independently controlled at timings which are different from each other. It is impossible that a clock signal is shared for the DA conversion in the transmission part at the time of transmission and for the AD conversion in the receiving part at the time of receiving.
FIG. 4 shows an AD converter in a receiving part of a conventional modem. As shown in FIG. 4, the receiving part of the conventional modem includes an AD converter (ADC) 20 which converts a received analog signal into a digital signal. A timing recovery unit 22 generates an estimated timing signal based on the digital signal output by the AD converter 20. The timing recovery unit 22 outputs a timing phase signal (tv) to the AD converter 20.
In the receiving part of the conventional modem of FIG. 4, the AD converter 20 requires the timing recovery unit 22 and a variable clock oscillator which are constructed with an external logic circuit. Further, it is impossible that a clock signal is shared for the DA conversion in the transmitting part of the conventional modem at the time of transmission and for the AD conversion in the receiving part of the conventional modem at the time of receiving. In the transmitting part (not shown in FIG. 4) of the conventional modem of FIG. 4, a DA converter for the DA conversion at the time of transmission requires a separate timing recovery unit and a separate variable clock oscillator. The separate variable clock oscillator outputs a clock signal to the DA converter, the timing phase of this clock signal being different from that determined by the estimated timing of the timing recovery unit 22 in the receiving part of the conventional modem of FIG. 4.
Japanese Laid-Open Patent Application No. 8-510100 (which is a national-phase publication of a translation of International Application No. PCT/US94/01755) discloses a resampling system in which the AD conversion is controlled at an estimated timing phase. The sequence of input samples after the AD conversion is subjected to smoothing so that the sampling rate is temporarily raised to a high sampling rate. The sequence of samples after the smoothing is subjected to the resampling. The temporarily raised sampling rate is lowered by the resampling in order to derive an estimated timing of the samples.
In the resampling method of the above publication, the smoothing is simply carried out but it is impossible to obtain a steep high-frequency cutoff characteristic. When the necessity arises, it is required to insert an additional lowpass filter in the resampling system. The characteristics obtained by the smoothing need corrections, and it is difficult to obtain an ideal frequency response even if an additional lowpass filter is provided. Such a lowpass filter will be complicated, and it is unavoidable that some characteristics are sacrificed.
In the resampling system of the above publication, a transversal filter of a type, which is constituted by a set of weighting coefficients, is used to carry out the interpolation. The amount of the computations on the transversal filter is relatively small, but it is necessary to provide a different set of weighting coefficients for each of interpolated timing phases. This makes the capacity of a ROM (read-only memory), which is needed for storing the different sets of weighting coefficients, significantly large. However, generally, the capacity of a storage device in a sampling system is limited. Hence, it is necessary to construct the resampling system of the above publication at the expense of the resolution of interpolated timing phases as the capacity of the storage of the weighting coefficients is limited.